1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for motor control, and more specifically to a semiconductor integrated circuit for controlling a motor at a constant speed by a PLL (phase locked loop) and PWM (pulse width modulation).
2. Description of Related Art
Referring to FIG. 10, there is shown a block diagram of one example of the prior art motor controlling semiconductor integrated circuit, which is generally designated with Reference Numeral 100. The semiconductor integrated circuit 100 is connected to a three-phase motor (spindle motor) 1 to be controlled, a reference oscillator 2 for generating a reference clock used for setting the number of revolution of the motor 1, a sense resistor 3 for detecting the current flowing through an armature coil at a stator side of the motor 1, and a DC power supply (not shown).
In the semiconductor integrated circuit 100, Reference Numerals 4, 5 and 6 designate output p-channel MOS transistors for controlling the timing of supplying the current to respective armature coils of the motor 1, and Reference Numerals 7, 8 and 9 denote output n-channel MOS transistors for controlling the amount of the current supplied to the respective armature coils of the motor 1. The transistors 4 and 7, 5 and 8, and 6 and 9 are connected in series, respectively. Respective sources of the transistors 4, 5 and 6 are connected in common to a power supply voltage terminal VDD, and respective sources of the transistors 7, 8 and 9 are connected in common to one end of the sense resistor 3 which is connected externally. The other end of the sense resistor 3 is connected to ground. A connection node between the transistors 4 and 7, a connection node between the transistors 5 and 8, and a connection node between the transistors 6 and 9 are connected to output terminals Out1, Out2 and Out3, respectively, which are connected to the armature coils of the motor 1, respectively.
Reference Numerals 10, 11 and 12 designate counter electromotive force comparators, which have their inverting input (xe2x88x92) connected through delay circuits 13, 14 and 15 to the armature coils of the motor 1, respectively, and their non-inverting input (+) connected in common to a neutral point of the motor 1.
Reference Numeral 16 denotes a phase comparing circuit having one input connected to an output of the reference oscillator 2 which is connected externally, and the other input connected to an output of the counter electromotive force comparator 10. Reference Numeral 17 indicates a low pass filter having an input connected to an output of the phase comparing circuit 16, and Reference Numeral 18 shows an integrator constituted of an operational amplifier having its non-inverting input (+) connected to an output of the low pass filter 17 and its inverting input (xe2x88x92) connected through a capacitor to an output of the operational amplifier itself and through a resistor to the source of the transistors 7, 8 and 9. Reference Numeral 19 designates a triangular wave generating circuit, and Reference Numeral 20 denotes a comparator having its non-inverting input (+) connected to an output of the integrator 18 and its inverting input (xe2x88x92) connected to an output of the triangular wave generating circuit 19.
Reference Numeral 21 indicates an output condition setting circuit receiving the output of the counter electromotive force comparators 10, 11 and 12, for outputting control signals T1, T2, T3, C1, C2 and C3 to a gate of the transistors 4, 5, 6, 7, 8 and 9, respectively.
As shown in FIG. 11, which is a logic diagram of one example of the phase comparing circuit 16, the phase comparing circuit 16 includes a digital phase comparator 22 composed of NAND gates and latches formed of NAND gates, a p-channel MOS transistor 23 and an n-channel MOS transistor 24 connected in series between the power supply voltage terminal VDD and the ground, and an inverter 25. One input xe2x80x9cRxe2x80x9d of the digital phase comparator 22 is connected to receive the reference clock CLK outputted from the reference oscillator 2 and the other input xe2x80x9cVxe2x80x9d of the digital phase comparator 22 is connected to the output of the counter electromotive force comparator 10. One output xe2x80x9cUxe2x80x9d of the digital phase comparator 22 is connected to a gate of the transistor 23, and the other output xe2x80x9cDxe2x80x9d of the digital phase comparator 22 is supplied through the inverter 25 to a gate of the transistor 24. A connection node between the transistors 23 and 24 is connected to the low pass filter 17.
Now, an operation of the semiconductor integrated circuit having the above mentioned construction will be described also with reference to FIG. 12.
By on-off controlling the transistors 4, 5, 6, 7, 8 and 9 so as to cause a current to flow through each two of the three-phase armature coils, a rotor rotates in the motor. The current direction is caused to cyclically take six current directions of Out3 to Out2, Out3 to Out1, Out2 to Out1, Out2 to Out3, Out1 to Out3, and Out1 to Out2, in the named order. A counter electromotive force voltage generated at the end of each armature coil at each time the current direction is changed, is supplied through the delay circuit 13, 14 or 15 to the counter electromotive force comparator 10, 11 or 12, respectively. The counter electromotive force comparators 10, 11 and 12 compare the respective counter electromotive force voltages with the potential of the neutral point of the armature coils, to generate rotor position detection signals P1, P2 and P3 as shown in (a) of FIG. 12 to the output condition setting circuit 21. At the same time, the position detection signal P1 (or P2 or P3) is supplied to the input xe2x80x9cVxe2x80x9d of the phase comparing circuit 16. Incidentally, since the six current directions are cyclically repeated as mentioned above, the delay circuits 13, 14 and 15 delay the phase of the counter electromotive force voltage generated at the end of the armature coils by 60 degrees, so that the next condition of the current direction is supplied through the counter electromotive force comparators 10, 11 and 12 to the output condition setting circuit 21 as the position detection signals P1, P2 and P3.
The timing of supplying the current to the respective armature coils of the motor 1, is controlled as follows. In response to the position detection signals P1, P2 and P3, the output condition setting circuit 21 generate timing signals T1, T2 and T3 as shown in (b) of FIG. 12. These timing signals T1, T2 and T3 are supplied to the gate of the transistors 4, 5 and 6, respectively, for the purpose of on-off controlling the transistors 4, 5 and 6, thereby to control the timings of supplying the current to the respective armature coils of the motor 1.
On the other hand, the amount of the current supplied to the respective armature coils of the motor 1 is controlled as follows: The reference clock CLK having the frequency as a desired rotational frequency of the motor 1 is supplied from the reference oscillator 2 to the input xe2x80x9cRxe2x80x9d of the phase comparing circuit 16, and at the same time, the position detection signal P1 is supplied to the input xe2x80x9cVxe2x80x9d of the phase comparing circuit 16. The phase comparing circuit 16 compares the phase of the position detection signal P1 with the phase of the reference clock CLK, to output a phase difference signal through the low pass filter 17 to the non-inverted input (+) of the operational amplifier of the integrator 18. A load current flowing through the armature coils of the motor 1 is converted by the sense resistor 3 into a voltage, which is supplied to the resistor of the integrator 18. The voltage integrated in the integrator 18 and the output of the triangular wave generating circuit 19 are supplied to the comparator 20, which generates a PWM signal to the output condition setting circuit 21. The output condition setting circuit 21 generates current control signals C1, C2 and C3 at timings as shown in (c) of FIG. 12, which are supplied to the gate of the transistors 7, 8 and 9, respectively. Thus, in combination of the on-off of the transistors 4, 5 and 6 with the on-off of the transistors 7, 8 and 9, the PWM outputs as shown in (d) of FIG. 12 are obtained at the output terminals Out1, Out2 and Out3, so that the current direction cyclically takes the six current directions in the above mentioned order, and therefore, the motor 1 rotates.
In the above mentioned construction, the PLL control is carried out to make the reference clock CLK of the reference oscillator 2 consistent with the frequency of the position detection signal P1 of the counter electromotive force comparator 10, and the duty of the PWM signal is determined on the basis of the output of the phase comparing circuit 16 and the detected voltage obtained from the sense resistor 3. As a result, the on-duty of the transistors 7, 8 and 9 is controlled so as to control the current flowing through the motor, thereby to control the motor at a constant speed.
Incidentally, Reference Numeral 26 in FIG. 12 designates a high frequency oscillation condition of the PWM signal for controlling the on-duty of the transistors 7, 8 and 9. For example, the position detection signal P1 is on the order of 300 Hz, and on the other hand, the PWM signal is on the order of 100 KHz.
However, the above mentioned prior art semiconductor integrated circuit has the following disadvantages:
(1) Since the semiconductor integrated circuit includes the low pass filter 17, the integrator 18, the triangular wave generating circuit 19 and the comparator 20, the circuit size becomes large and therefore a necessary chip area is large.
(2) Since the transistors 7, 8 and 9 are on-off switched on the order of for example 100 KHz for each phase on the basis of the PWM control, switching noises are inevitably involved.
(3) Since the sense resistor 3 is connected in series with the transistors 4, 5 and 6 and the transistors 7, 8 and 9, a power loss occurs in the sense resistor 3, and therefore, in order to reduce the power loss in the whole of this series circuit, the transistors 4, 5, 6, 7, 8 and 9 having a small on-resistance become necessary, resulting in a further increased chip area.
Accordingly, it is an object of the present invention to provide a motor controlling semiconductor integrated circuit which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a motor controlling semiconductor integrated circuit which can reduce the necessary circuit size, and can carry out the PWM control with a single pulse, and which no longer requires the sense resistor.
The above and other objects of the present invention are achieved in accordance with the present invention by a motor controlling semiconductor integrated circuit for controlling a motor by a PLL control, comprising output transistors for driving a motor, a position detecting means detecting a rotational position of a rotor in the motor, for generating a position detection signal, a phase comparing means comparing the position detection signal with a reference clock. For generating a phase difference detection signal, and means receiving the phase difference detection signal, for controlling an on-duty of the output transistors on the basis of a duty of the phase difference detection signal.
With the above mentioned arrangement, since the low pass filter, the integrator, the triangular wave generating circuit and the comparator, which were required in the prior art semiconductor integrated circuit, are no longer necessary, the circuit size can be reduced, and therefore, a necessary chip area can be reduced. In addition, since the output transistors are on-off switched at a low frequency on the order of 300 Hz, similar to the frequency of the position detection signal, switching noises can be greatly reduced. Furthermore, since the constant speed control can be carried out without monitoring the current of the motor by means of the sense resistor, it is no longer necessary to pay attention the voltage drop across the sense resistor, and therefore, the output transistors having an on-resistance larger than that of the prior art can be used, resulting in a reduced chip area for these transistors.
Specifically, the motor is a three-phase motor, and the position detecting means includes three counter electromotive force comparators each comparing a counter electromotive force generated in an armature coil of a corresponding phase when the motor is rotating, with a neutral point potential of the armature coils, for generating the position detection signal for the corresponding phase. The reference clock is set to have a frequency which is three times a desired rotational frequency of the motor. The position detection signals are supplied to a synthesis circuit for generating a synthesis signal having a frequency which is three times the frequency of the position detection signals, and the phase difference detection signal is supplied to the output transistors through an output condition setting circuit which frequency-divides the phase difference detection signal into the frequency of the position detection signals.
For example, the synthesis circuit includes three two-input NAND gates each receiving the outputs of each different two of the counter electromotive force comparators, and a three-input NAND gate receiving an output of the two-input NAND gates.
In addition, if two phase comparing circuits are provided in parallel, one of which directly receives the synthesis signal and the reference clock, and the other of which receives the synthesis signal and the reference clock through inverters, respectively, it is possible to control the output transistors in the on-duty range of 0 to 100%.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.